Welcome to Francis Academic Press

International Journal of Frontiers in Engineering Technology, 2024, 6(1); doi: 10.25236/IJFET.2024.060120.

Research on high-speed communication mechanism of time-triggered network based on RGMII

Author(s)

Changhao Wang, Tiantian Li

Corresponding Author:
Tiantian Li
Affiliation(s)

School of Electronic Information and Artificial Intelligence, Shaanxi Uninersity of Science & Technology, Xi'an, China

Abstract

With the rapid development of time-triggered network, the demand for its network performance is getting higher and higher. The transmission mechanism of time-triggered network is time-triggered mechanism, which is used to study the high-speed communication of time-triggered network. This paper proposes a high-speed communication design scheme for time-triggered network based on RGMII interface: time-triggered network transmission control module, FPGA board for time-triggered network transmission control, time-triggered encapsulation and analysis module for communication with host computer, configuration module for parameter configuration, cyclic redundancy check module for data error check. The communication between PHY layer and MAC layer is carried out by RGMII interface. Finally, simulation verification and upper board verification are carried out to realize the high-speed transmission of time-triggered network based on RGMII interface.

Keywords

Time-triggered network, SAE AS6802, High speed communication

Cite This Paper

Changhao Wang, Tiantian Li. Research on high-speed communication mechanism of time-triggered network based on RGMII. International Journal of Frontiers in Engineering Technology (2024), Vol. 6, Issue 1: 125-130. https://doi.org/10.25236/IJFET.2024.060120.

References

[1] Gao P.F. Design of the Time-Triggered Ethernet Switch [D]. Xidian University, 2014.

[2] Zhou, J. Design and Implementation of AS6802 Synchronization Protocol Based on Time-triggered Ethernet [D]. Xidian University, 2018.

[3] H, Kopetz, G, Grunsteidl. TTP-A protocol for fault-tolerant real-time systems [J]. Computer, 1994, 27(1): 14-23.

[4] H, Kopetz, G, Bauer. The Time-Triggered Architecture [J]. IEEE, 2003, 91(4): 112-126.

[5] H, Kopetz, A, Ademaj, P, Grillinger. and K, Steinhammer. The Time-Triggered Ethernet (TTE) Design[C]// Eighth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing, 2005: 22-33.

[6] SAE AS6802. Time-Triggered Ethernet[S]. SAE Aerospace Standard, 2011.

[7] Lan, J., Zhu, X.F., Chen, Y. and Li, Q. Research on Time-Triggered Ethernet standards [J]. Aeronautic Standardization & Quality, 2013(05): 24-27+56.

[8] Zhang, K. Research on High Precision Clock Synchronization Technology of Time-Triggered Ethernet [D]. Beijing University of Technology. 2020.

[9] Lan, J., Xiong, H.G. and Li, Q. Clock synchronization fault-tolerance in Time-triggered Ethernet [J]. Computer Engineering and Design, 2015, 36(01): 11-16.

[10] Yang, J.X., Xu, Y.J., He, F. and Liu,Z.D. Research on Influence of Clock Synchronization Accuracy to TTE Real-Time Performance[J]. Electronics Optics & Control, 2016, 23(08): 33-38.

[11] Zhang, Y.J., Xiong, H.G., Liu, Z.D. and Li, Z. Application of TTE Communication Technology in Avionics System [J]. Electronics Optics & Control, 2015, 22(05): 49-53.

[12] Steiner, W. TTEthernet specification [J]. TTTech Computertechnik AG, Nov, 2008.

[13] Li, Z.W. The Research of Time Triggered Ethernet based on Network Calculus [D]. University of Electronic Science and Technology of China, 2013.

[14] Dong, J.W. Time Triggered Ethernet Accelerating Avionics Interconnection [J]. Electronics Optics & Control, 2016, 23(02): 74-78.