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Academic Journal of Engineering and Technology Science, 2022, 5(10); doi: 10.25236/AJETS.2022.051004.

Analysis on heat transfer characteristics of integrated circuit silicon chip package based on finite element model

Author(s)

Shuaiyi Pan1, Longlong Wu2

Corresponding Author:
Shuaiyi Pan
Affiliation(s)

1Dalian University of Technology, Dalian, 116000, China

2Xinglin College of Nantong University, Nantong, 226000, China

Abstract

The heating problem of components in integrated circuits has become an important factor affecting the service life and reliability of chips and the whole circuit. In recent years, the study of thermal effects in circuit design and packaging process has become an important topic. In this article, we use comsol software model for integrated circuits, close to the surface of the voltage regulator on simulation circuit boards silicon chips and heat condition of components, each part drawing three dimensional temperature distribution, by changing the voltage regulator for heating power, analysis of the voltage regulator in a certain position in different heating situations on the circuit chip as the core of the influence of the temperature of the parts, Finally, the safe operating range of integrated circuit is obtained without affecting the life of each device. In the simulation process, the thermal thin approximation and grid processing are used, and the temperature distribution map obtained is smooth and continuous, and the circuit structure is fully simulated, which can provide guidance and suggestions for real IC packaging.

Keywords

Heat Transfer; COMSOL; encapsulation; finite element mesh; temperature field

Cite This Paper

Shuaiyi Pan, Longlong Wu. Analysis on heat transfer characteristics of integrated circuit silicon chip package based on finite element model. Academic Journal of Engineering and Technology Science (2022) Vol. 5, Issue 10: 20-25. https://doi.org/10.25236/AJETS.2022.051004.

References

[1] Shen Haidong, Zhang Ze, Chen Kewen, et al. Thermal analysis and evaluation method of typical chip packaging based on double thermal resistance model [J]. Equipment Environmental Engineering, 2018. 15 (7): 10-14. 

[2] Wang Hongwei. Thermal stress Analysis of IC Chip package [J]. Journal of Xinyu College, 2006. 11 (4): 87-90. 

[3] Savidis, Ioannis, Vaisband, Boris, Friedman, Eby G. Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits[J]. IEEE transactions on very large scale integration (VLSI) systems, 2015,23(10):2077-2089..

[4] Lian Xingfeng, Su Jilong. Thermal effect of package and influence of bonding layer on stress and strain of microchip [J]. Mechatronics, 2012. Jade 35 (6): 33-36.

[5] Niu Ligang, Yang Daoguo, Li Li. Effect of EMC material parameters on thermal stress of microelectronic packaging devices [J]. Journal of functional Materials and Devices, 2010. J 16 (4): 384-388.

[6] Du Bing, Yin Jinghua, Liu Xiaowei. Thermal stress analysis of laminated chip package under power load [J]. Journal of Harbin University of Technology, 2007. Journal. 12 (5): 57-60.

[7] Jin Y X. Thermal-structure Numerical Simulation analysis and Optimization design of Integrated circuit chip packaging [D]. Dalian University of Technology, 2004.

[8] Li Ang, Yang Cheng, Jia Yige, Li Dan, Li Yong, Hou Rongbin, Wu Zhiqiang, Huang Wenna. Simulation analysis of heat dissipation of power plug-in based on Icepak [J]. Instrument user,2021,28(05):56-59.

[9] Fu J Y. Research on thermal optimization of TSV cluster structure based on 3D integrated circuit [D]. Beijing University of Technology, 2017.