Ring oscillator is an important structure of digital chip, and the optimized design of ring oscillator becomes especially important with the booming development of chip manufacturing industry. In this paper, a ring oscillator power consumption optimization model and a multi-project wafer circuit installation model are constructed to provide an effective theoretical optimization model support for the actual production life of digital chips. Under the premise of ensuring the minimum overall power consumption, the total power consumption of the ring oscillator is used as the objective function, and the particle swarm optimization algorithm is used to solve the number of inverters of the oscillator and the Length of the transistor is 213nm and the minimum total power consumption of the ring oscillator is 0.8 mW. Moreover, the jigsaw puzzle idea is used as the circuit design concept, and the maximum area of the seventh chip is obtained after the reasonable placement of six fixed area chips 0.554mm×1.774mm.

Minqi Li, Yuecheng Wang, Wensheng Guo. Optimization model design of multi-factor nonlinear ring oscillator. International Journal of Frontiers in Engineering Technology (2022), Vol. 4, Issue 10: 22-27. https://doi.org/10.25236/IJFET.2022.041004.

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