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Academic Journal of Materials & Chemistry, 2023, 4(7); doi: 10.25236/AJMC.2023.040711.

Prospect for Overcoming Sub-threshold Slope Degradation with NC-FETs

Author(s)

Zifan Xu

Corresponding Author:
Zifan Xu
Affiliation(s)

Glasgow College, University of Electronic Science and Technology of China (UESTC), Chengdu, 611731, China

Abstract

For conventional MOSFETs, with the reduction in the thickness of silicon dioxide, the value of subthreshold swing has reached 60 mV/dec, a minimum constrained by thermodynamics. Hence, further scaling of transistor necessitates novel approaches while maintaining high performance. So far, there are three main parallel paths of overcoming sub-threshold degradation, which are enhancing gate control, using the band-to-band tunneling (BTBT) mechanism and change the capacitance of oxide layer, the corresponding solutions are FinFET/gateall-around FET(GAAFET), tunnel FET(TFET) and negative capacitance field-effect transistor (NC-FET), respectively. This paper mainly explores the feasibility of utilization of NC-FETs as a promising solution with the Ferroelectric-Dielectric materials, thereby evaluating the prospect of NC-FETs as a potential candidate to continue reducing sub-threshold slope degradation. Several critical issues of NC-FETs that are not favorable to application due to their intrinsic features, such as hysteresis, are analyzed, including the latest research efforts aimed at tackling those problems.

Keywords

NCFET, Ferroelectrics, Hysteresis

Cite This Paper

Zifan Xu. Prospect for Overcoming Sub-threshold Slope Degradation with NC-FETs. Academic Journal of Materials & Chemistry (2023) Vol. 4, Issue 7: 69-76. https://doi.org/10.25236/AJMC.2023.040711.

References

[1] C. Ortega, J. Tse, and R. Manohar, “Static power reduction techniques for asynchronous circuits,” in 2010 IEEE Symposium on Asynchronous Circuits and Systems, pp. 52–61, 2010.

[2] Q. Xie, J. Xu, and Y. Taur, “Review and critique of analytic models of mosfet short-channel effects in subthreshold,” IEEE transactions on electron devices, vol. 59, no. 6, pp. 1569–1579, 2012.

[3] M. H. Bhuyan, “A review of recent research works on negative capacitance field effect transistor,” Southeast University Journal of Science and Engineering (SEUJSE), vol. 1630, pp. 36–44, 1999.

[4] H.-S. Wong, D. J. Frank, and P. M. Solomon, “Device design considerations for double-gate, ground-plane, and single-gated ultra-thin soi mosfet’s at the 25 nm channel length generation,” in International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217), pp. 407–410, IEEE, 1998.

[5] P. Solomon, K. Guarini, Y. Zhang, K. Chan, E. Jones, G. Cohen, A. Krasnoperova, M. Ronay, O. Dokumaci, H. Hovel, et al., “Two gates are better than one [double-gate mosfet process],” IEEE circuits and devices magazine, vol. 19, no. 1, pp. 48–62, 2003.

[6] R. S. Pal, S. Sharma, and S. Dasgupta, “Recent trend of finfet devices and its challenges: A review,” in 2017 Conference on Emerging Devices and Smart Systems (ICEDSS), pp. 150–154, IEEE, 2017.

[7] D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, “A fully depleted lean-channel transistor (delta)-a novel vertical ultra thin soi mosfet,” in International Technical Digest on Electron Devices Meeting, pp. 833–836, IEEE, 1989.

[8] M. Jurczak, N. Collaert, A. Veloso, T. Hoffmann, and S. Biesemans, “Review of finfet technology,” in 2009 IEEE international SOI conference, pp. 1–4, IEEE, 2009.

[9] S. M. Turkane and A. Kureshi, “Review of tunnel field effect transistor (tfet),” International Journal of Applied Engineering Research, vol. 11, no. 7, pp. 4922–4929, 2016.

[10] T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-gate strained-ge heterostructure tunneling fet (tfet) with record high drive currents and 60mv/dec subthreshold slope,” in 2008 IEEE International Electron Devices Meeting, pp. 1–3, IEEE, 2008.

[11] J. C. Wong and S. Salahuddin, "Negative Capacitance Transistors," in Proceedings of the IEEE, vol. 107, no. 1, pp. 49-62, Jan. 2019, doi: 10.1109/JPROC.2018.2884518.

[12] M. Ershov, H. Liu, L. Li, M. Buchanan, Z. Wasilewski, and A. K. Jonscher, “Negative capacitance effect in semiconductor devices,” IEEE Transactions on Electron devices, vol. 45, no. 10, pp. 2196–2206, 1998.

[13] H. Wang, M. Yang, Q. Huang, K. Zhu, Y. Zhao, Z. Liang, C. Chen, Z. Wang, Y. Zhong, X. Zhang, and R. Huang, “New insights into the physical origin of negative capacitance and hysteresis in ncfets,” in 2018 IEEE International Electron Devices Meeting (IEDM), pp. 31.1.1–31.1.4, 2018.

[14] S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Letters, vol. 8, no. 2, pp. 405–410, 2008. PMID: 18052402.

[15] M. Hoffmann, S. Slesazeck, and T. Mikolajick, “Progress and future prospects of negative capacitance electronics: A materials perspective,” APL Materials, vol. 9, no. 2, 2021.